Retired 8/2022
Blogging, writing, music, improv, acting, podcasts, technology projects, astronomy, travel…
Cerebras Systems, 9/2019-8/2022
Senior Manager, Software Stack
Managed the team which developed software to map deep learning networks to a compute fabric containing up to 850,000 cores. Drove bringup of computer vision networks.
Intel PSG Architecture, 10/2017-9/2019
Architect, Senior Manager, EXAScale computing R&D
Architectural analysis. Managed the team which provided a spatial back-end for the compiler stack.
Intel PSG Design Automation, 1/2016-10/2017
Director, Design Automation
Lead the global PSG Design Automation team. Deliver tools and flows for design of FPGA silicon. Front end through layout and tapeout.
Altera Design Automation, 4/2011-12/2015
Director, Design Automation 4/2015-12/2015
Lead the global Altera Design Automation team. Deliver tools and flows for design of FPGA silicon. Front end through layout and tapeout.
Senior Manager, Design Automation 4/2011-4/2015
Front End DA Manager, 4/2011-4/2012, Global DA Manager 4/2012-4/2015
AMD, 4/2003-4/2011
Senior Manager, CAD Architecture, Infrastructure, Custom Design 7/2008-4/2011
Chair CAD Architecture committee, oversee transition to Open Access based custom design. Open Access Coalition representative and Chairman. Maintain and enhance CAD infrastructure and custom design and layout flow.
Senior Manager, CAD Platform 9/2004-7/2008
Manage development of the entire CAD platform for the Bulldozer microprocessor generation.
SMTS, CAD infrastructure developer, 4/2003-9/2004
Improvement to K8 CAD flow. Full chip build, pin flow, visualization tools. Implemented flow changes to enable dual core K8 development.
Sandcraft, 12/1998-4/2003
Director, CAD 7/2000-4/2003
Responsible for all CAD flow development and tool acquisition.
MTS, 12/2998-7/2000
CAD flow development. Synthesis, Placement, Routing, power strapping, abstract generation.
MMC Networks, 9/1997-12/1998
Physical design engineer and CAD flow developer
Bring up of COT physical design flow, Base array generation, ECO flow
HaL Computer Systems, 4/1991-9/1997
Physical Tools Manager, 5/1996-9/1997
Develop a chiplet based floorplanning and pin management tool. Manage the team providing placement routing, power strapping, power analysis, and timing tools.
Manager, I/O Hardware, 5/1994-5/1996
Manage the I/O Subsystem team for the R2 generation of products.
I/O ASIC Lead, 4/1991-5/1994
Develop ASIC methodology and flow (Verilog, Synopsys synthesis). Architecture and design of the R1 I/O subsystem. Design of the LIM ASIC.
SMOS Systems, 9/1990-4/1991
SMTS
Architect for a single chip 3d graphics geometry engine.
Data General Corp., 5/1981-9/1990
MV30000 I/O Subsystem Manager
Team lead, Architecture and design of the TIOGA ASIC and daughter card
MV40000 Data Unit Manager
Team lead, board and ASIC design for the data cache
MV4000 floating point unit
Microcode and board level logic design for a single board FPU
Microcode, Falcon project
Multiply, divide, queue instructions